We explained above that the output of sequential logic systems depends on the input of the system and the state of

his previous. So, these systems need to use a memory element for it

maintaining the previous state of the system, bistables are used for this purpose. A bistable can

maintain the state of the system until an input variable tells the one to change

his condition. A bistable contains two inputs (x, y), an hour signal and two outputs, one of which is the output

the normal of the system z while the other is the output complement (z̅). The output of a bistable is either 0 or 1.

(figure 2). We have several types of bistables: SR, T, D and JK, which we will explain below. The SR bistable can be considered as a simpler bistable. It is usually a memory device

one-bit which has two inputs, one that makes the system “SET” (ie gives the output “1”) and is marked with S and

the other that resets (RESET) the system (i.e. gives the output “0”) and is marked with R. For this reason, the bistable is known

as bistable SR (Set-Reset). This bistable gives the future state Q + in function of the current state

of system and inputs S and R.

The SR bistable diagram is given in Figure 2. The truth table of this bistable consists of 3

input (S, R and Q) and an output Q +

, which depends on the three inputs of the system. (Table 2 and Table 3). The state table is a system layout which gives all possible combinations of

inputs, internal and future states and system output. For more complex systems

constructing the state table is difficult. The condition diagram is a useful tool for

express the requirements of the system graphically, before constructing the state table. it

contains the same information as the tables of states, but expressing the transition of states of

next in the form of a graph.

The condition diagram consists of the joints (in the shape of a circle) and the directed arches which connect

nodes with each other and indicate the transition to the transition between system states. In the diagram

of conditions:

. The number of nodes is the same as the number of system states. Each condition is determined

a label (tag, or binary code) marked inside the circle.

. The number of arcs arising from a node is 2


, where n is the number of different inputs to the system.

For example, if the system has only one H input from one node two arcs will emerge (21 = 2), one

for the input H = 0 and the other for the input H = 1.

The steps for building a sequential system (figure 8) are:

. The first step in designing a sequential system is to determine the problem.

. In the second step, you can proceed directly to the construction of the state table. But for occasions

the more complex it is the easier it is to first construct the state diagram, and then the

proceeds to the construction of the condition table.

. The third step is simply the table of states, reducing the number of internal states

that the system has. Two states can be simplified with each other when they are able to

future and same exit. The table at the end of this step is known as the state table

simplified. In the fourth step, determine the states, encoding them with a binary code. Must

care must be taken that the coding is unique to each condition. Usually for status coding

the reflected code is used, so that each internal state changes from the state

offspring with only one bit. The state table, in which the states are encoded, is known

as the coded state table.

 In the fifth step, the functions of determining the signals of the above are added to the above table.

bistable with which the synchronous sequential system will be constructed.

 From the fifth step table the logical output functions and bistable signals are extracted.

. The seventh step is to build the system circuit. Building the state diagram always starts with an initial state. In the initial state it is stored

the beginning of the distinction of a sequence or the input which does not serve as the beginning of the sequence but as its reset. in

our example, we seek to distinguish a 4-bit sequence – 1 0 1 1. Since the sequence

ours starts with bit ‘1’, then the initial state of the diagram will be taken that state which resets

the required sequence, i.e. the beginning of the ‘0’ sequence. We label this condition with the letter A and

consider that this is the initial which has a safe (or saves) a bit equal to ‘0’ From the initial state we will have output arcs depending on the input (0 or 1). If the input is 0, the arc

will return to state A (as we have not yet started with the required sequence). If the input

is 1, then we have to save it (to recognize sequence 1011) by going to a state

new which we will label with the letter B. Condition B will be the state where we have stored

the first ‘1’ bit to start the sequence. In both arcs the output is 0, this is because we have not yet reached

4 bit sequence.

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From the last lecture we have the design and construction of a synchronous sequential system, the Diver of sequences. Usually when designing a sequential system, solving the problem can lead to the appearance of excessive internal states. So the diagram or table of states can contain more condition than the […]

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